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Package Types not to scale. This application is not tested but ensured by characterization.
Mold Draft Angle Bottom. High level output voltage.
8K/16K 5.0V Microwire Serial EEPROM
Data output delay time. The higher the current sourcing capability of. CLK cycles are not required during the self-timed.
Note 2 Note 3. I CC write Write current.
I CC read Read current. After power-up, the device is automatically in the. Opcodes, address and data bits are clocked in. Low level output voltage. If CS is low, the internal. These clock cycles are. Pb-free topside mark is same; Pb-free.
93C86 – Memory – Memory
The Serial Clock is used to synchronize the communi. High level input voltage. DO at logical “0” indicates that program. If CS is brought low during a program cycle, the. The entire 93XX Series is. Chip select low time.
93C86 PDF Datasheet浏览和下载
All modes of operation are inhibited when V CC is below. For proper operation, ORG. Temperature grade is marked on line 2. Program Datadheet pin to write protect the entire.
Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. CS is brought low.
Sequential read is possible when. T SV is relative to CS. Exposure to maximum rating conditions for extended periods. Mold Draft Angle Top.
Data output disable time. All Programming modes must be. Advanced CMOS technology makes.